Overview
IEC 60191-6:2009 is an international standard published by the International Electrotechnical Commission (IEC) that provides general rules for preparing outline drawings of surface-mounted semiconductor device packages. It is part 6 of the IEC 60191 series, focused on the mechanical standardization of semiconductor devices.
This third edition updates and supersedes the 2004 edition with significant revisions to broaden scope and refine technical details, particularly for ball grid array (BGA) packages. It specifically covers discrete surface-mounted semiconductor devices with lead counts of 8 or more and integrated circuits classified as form E according to IEC 60191-4.
By standardizing the preparation of outline drawings, IEC 60191-6 helps manufacturers, designers, and engineers ensure clear, uniform mechanical specifications that support global interoperability and facilitate device assembly, testing, and quality assurance.
Key Topics
- Scope and coverage: Applies to surface-mounted semiconductor devices with lead counts ≥ 8 and integrated circuit packages in form E classification.
- Outline drawing preparation: Defines consistent formats, symbols, dimensions, and projection methods for package outlines, enabling precise communication.
- Geometrical drawing rules: Specifies geometrical tolerancing and dimensional specification requirements ensuring device fit and functionality based on ISO 1101.
- Terminal projection zone: Introduces the concept of the seating plane and reference plane, vital for defining the terminal projection zone for mounting leads.
- Ball grid array (BGA) revisions: Harmonizes previously two BGA types under a single geometrical drawing format, simplifying the design and documentation process.
- Supplementary guidelines: Includes annexes with informative illustrations and table formats to assist in drafting compliant outline drawings.
Applications
IEC 60191-6:2009 is essential for professionals involved in the design, manufacturing, and quality control of semiconductor devices, particularly:
- Semiconductor manufacturers who produce surface-mounted devices requiring consistent mechanical drawings for tooling and assembly.
- Component designers and engineers tasked with creating standardized device packages for PCB integration.
- Quality assurance teams ensuring compliance with international mechanical standards during production inspections.
- Contract manufacturers and assemblers who rely on accurate mechanical outlines for pick-and-place operations, soldering, and packaging.
- Equipment manufacturers developing test and measurement devices compatible with standardized semiconductor package outlines.
By adhering to IEC 60191-6, organizations can reduce risks of mechanical inconsistencies, improve device interchangeability, optimize manufacturing processes, and enhance international supply chain collaboration.
Related Standards
- IEC 60191-1:2007 – Provides general rules for preparation of outline drawings for discrete semiconductor devices, forming a foundational base complemented by part 6.
- IEC 60191-3 – Addresses specific rules and requirements for surface-mounted semiconductor devices with fewer leads, cooperating with IEC 60191-6.
- IEC 60191-4:2002 – Details coding systems and classification into forms of package outlines, including the form E classification referred to in IEC 60191-6.
- ISO 1101:2004 – Covers geometrical product specifications and tolerancing essential for defining form, orientation, and location tolerances in semiconductor package drawings.
Adopting IEC 60191-6:2009 enables consistent, high-quality mechanical documentation of surface-mounted semiconductor device packages, advancing global standardization and facilitating seamless technological integration across the electronics industry.
Open preview (PDF)Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
