IEC 60191-6-6:2001 PDF

Mechanical standardization of semiconductor devices - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA)

First page of standard IEC 60191-6-6:2001

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Title (English):

IEC 60191-6-6:2001

Document status:: Active
Format:: Electronic (PDF)
Number of pages:: 12
Publication date:: March 22, 2001
Edition:: IEC IS 60191 edition 1 version 1
ICS:: 31.080.01

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Description (English):

IEC 60191-6-6:2001 provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch land grid array (hereinafter called FLGA) whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is square.

Technical details

Technical committee: SC 47D - Semiconductor devices packaging
SKU: IEC 60191-6-6:2001

Abstract

Overview

IEC 60191-6-6:2001 is an IEC design guide for the mechanical standardization of fine-pitch land grid array (FLGA) surface-mounted semiconductor packages. It defines common outline drawings, dimensional rules and classification for square-bodied FLGA packages whose terminal pitch (e) is ≤ 0.80 mm and whose terminal height is ≤ 100 µm. The standard aims to promote interchangeability and consistent outline documentation for FLGA package families.

Key topics

Scope and classification
- Applies to square FLGA packages with terminal pitch e = 0.80, 0.65, 0.50, 0.40 mm.
- Material designations: P-FLGA (plastic/interposer resin) and C-FLGA (ceramic).
- Package body types: flanged type and type of real chip size.
Outline drawing rules
- Defines datums (A, B, primary datum S) and seating plane (by least squares of spherical crowns of terminals) for consistent drawing and measurement.
- Specifies visible index zones, terminal arrays and geometry annotations.
Dimensional groups and limits
- Grouped dimension tables for: mounting/interchangeability, mounting/gauging, automated handling, and informational dimensions.
- Typical dimensional parameters include body sizes (D, E), terminal pitch (e), terminal diameter/land size (b, b2), offsets (ZD, ZE) and overhang rules.
Ball/matrix guidance
- Table-based guidance on maximum terminal matrix sizes and recommended matrix families for each pitch (examples for 4×4 up to 26×26 depending on e).
Purpose
- Standardizes outline drawings to support PCB footprint design, pick-and-place handling, gauging and interchangeability among manufacturers.

Applications

Who uses IEC 60191-6-6 and why:

Package designers - to create compliant FLGA outline drawings and select matrix/land layouts.
PCB layout engineers - to design footprints and land patterns compatible with standardized FLGA outlines.
Assembly/test engineers - to validate mounting/gauging, automated handling and seating plane requirements.
Procurement / quality teams - to specify interchangeability and acceptance criteria for FLGA components.
Standards and compliance specialists - for cross-referencing with the IEC 60191 family.

Related standards

IEC 60191 (all parts) - broader mechanical standardization of semiconductor devices.
Drafting follows ISO/IEC Directives, Part 3 as noted in the publication.

Keywords: IEC 60191-6-6, FLGA, fine-pitch land grid array, surface mounted semiconductor packages, outline drawings, terminal pitch, P-FLGA, C-FLGA, package interchangeability.

Related standards

Mentioned in the description and other IEC standards

Abstract

Overview

Key topics

Scope and classification
- Applies to square FLGA packages with terminal pitch e = 0.80, 0.65, 0.50, 0.40 mm.
- Material designations: P-FLGA (plastic/interposer resin) and C-FLGA (ceramic).
- Package body types: flanged type and type of real chip size.
Outline drawing rules
- Defines datums (A, B, primary datum S) and seating plane (by least squares of spherical crowns of terminals) for consistent drawing and measurement.
- Specifies visible index zones, terminal arrays and geometry annotations.
Dimensional groups and limits
- Grouped dimension tables for: mounting/interchangeability, mounting/gauging, automated handling, and informational dimensions.
- Typical dimensional parameters include body sizes (D, E), terminal pitch (e), terminal diameter/land size (b, b2), offsets (ZD, ZE) and overhang rules.
Ball/matrix guidance
- Table-based guidance on maximum terminal matrix sizes and recommended matrix families for each pitch (examples for 4×4 up to 26×26 depending on e).
Purpose
- Standardizes outline drawings to support PCB footprint design, pick-and-place handling, gauging and interchangeability among manufacturers.

Applications

Who uses IEC 60191-6-6 and why:

Package designers - to create compliant FLGA outline drawings and select matrix/land layouts.
PCB layout engineers - to design footprints and land patterns compatible with standardized FLGA outlines.
Assembly/test engineers - to validate mounting/gauging, automated handling and seating plane requirements.
Procurement / quality teams - to specify interchangeability and acceptance criteria for FLGA components.
Standards and compliance specialists - for cross-referencing with the IEC 60191 family.

Related standards

IEC 60191 (all parts) - broader mechanical standardization of semiconductor devices.
Drafting follows ISO/IEC Directives, Part 3 as noted in the publication.

Keywords: IEC 60191-6-6, FLGA, fine-pitch land grid array, surface mounted semiconductor packages, outline drawings, terminal pitch, P-FLGA, C-FLGA, package interchangeability.

IEC 60191-6-6:2001 PDF

Technical details

Abstract

Overview

Key topics

Applications

Related standards

Related standards

Abstract

Overview

Key topics

Applications

Related standards

Related standards

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