Overview - IEC 61691-1-1:2023 (VHDL Language Reference Manual)
IEC 61691-1-1:2023 is the international Language Reference Manual (LRM) for the VHSIC Hardware Description Language (VHDL). Published as an IEC/IEEE dual-logo standard and aligned with IEEE Std 1076-2019, this edition (Edition 3.0, 2023-10) formally defines the syntax and semantics of VHDL. The title references VHSIC (Very High Speed Integrated Circuits), the U.S. program that motivated the language’s development. The standard provides normative rules designers and tool vendors use to ensure consistent modelling, simulation, synthesis and verification of digital hardware.
Key topics and technical requirements
The standard specifies detailed language elements, with major technical areas including:
- Design entities and configurations: entity declarations, architecture bodies, configuration declarations.
- Subprograms and packages: subprogram declarations/bodies, overloading, resolution functions, package bodies and instantiation.
- Types and declarations: scalar/composite/access/protected types, string representations, subtype and object declarations.
- Statements and modelling styles: sequential statements (if, case, loop, wait), concurrent statements (process, concurrent signal assignment, component instantiation), generate statements.
- Names, expressions and operators: simple/selected/indexed/slice names, operator definitions, static and universal expressions.
- Scope, visibility and analysis: declarative regions, use clauses, context clauses, order of analysis.
- Elaboration and execution model: elaboration of design hierarchies, dynamic elaboration, and model execution rules.
- Lexical elements and conformance: character set, identifiers, literals, plus normative references and conformance requirements for tools and implementations.
These topics define both syntactic rules and formal semantic behaviour, which are essential for interoperable EDA toolchains.
Applications and who uses this standard
IEC 61691-1-1:2023 is used by:
- FPGA and ASIC designers for writing synthesizable and testable RTL models in VHDL.
- Verification engineers for simulation, assertions, testbenches and formal verification.
- EDA tool vendors (simulators, synthesizers, linters, formal tools) to ensure standards-compliant parsing and semantics.
- Academia and training for courses on digital design and hardware description languages.
- Standards and compliance teams ensuring cross-tool compatibility and correct implementation of VHDL features.
Typical applications include hardware modelling, system-level simulation, RTL synthesis, verification environments, and multi-vendor tool integration.
Related standards and resources
- IEEE Std 1076-2019 - the corresponding IEEE standard referenced by this LRM.
- Obtain official copies and updates from the IEC webstore (webstore.iec.ch) or IEEE. The IEC maintains corrigenda and amendments; always use the latest edition for compliance.
Keywords: IEC 61691-1-1:2023, VHDL, IEEE Std 1076, VHDL Language Reference Manual, hardware description language, VHSIC, digital design, FPGA, ASIC, EDA tools, simulation, synthesis, verification.
