Overview
IEC 61691-6:2021 (IEC/IEEE Std 1076.1) defines the VHDL Analog and Mixed-Signal Extensions - commonly known as VHDL‑AMS. This double‑logo IEC‑IEEE standard extends the base VHDL language (IEC 61691‑1‑1 / IEEE 1076) to provide a harmonized hardware description language for the description, modeling and simulation of analog, digital and mixed‑signal systems. IEC 61691‑6:2021 covers language syntax, semantics and simulation semantics required for accurate behavioral and structural AMS modeling.
Key Topics and Technical Scope
The standard systematically specifies the language constructs and simulation behavior needed for AMS design. Key topics include:
- Design entities and configurations - entity declarations, architectures and configuration mechanisms for hierarchical AMS designs.
- Subprograms and packages - procedures, functions, overloading, packages and instantiation for reusable analog/digital models.
- Types and natures - scalar/composite types, access and protected types, plus natures for analog quantity semantics.
- Declarations and interfaces - port and signal declarations, interface modes and connectivity for mixed‑signal blocks.
- Expressions and statements - sequential and concurrent statements, signal and variable assignment, procedural constructs tailored to AMS behavior.
- Architecture statements and elaboration - processes, component instantiation, generate statements and elaboration/execution semantics for simulation.
- Simulation control and specifications - attributes, configuration, disconnection and step limit specifications to govern mixed‑signal simulation.
These topics (detailed in the standard’s table of contents) define both the language features and conformance rules necessary for interoperable tool support.
Practical Applications and Who Uses It
IEC 61691‑6:2021 is essential for professionals and organizations that need standardized AMS modeling and simulation:
- Analog and mixed‑signal IC designers - behavioral modeling of amplifiers, ADC/DAC, PLLs, RF front‑ends.
- SoC and system engineers - integration and co‑simulation of digital logic with analog blocks and sensors.
- EDA tool vendors - implementing VHDL‑AMS parsers, simulators and co‑simulation frameworks.
- Verification and validation teams - system‑level verification, regression testing and analog/digital interaction checks.
- Academia and research - teaching analog/digital co‑design and developing reusable AMS models.
Using VHDL‑AMS enables consistent description of continuous‑time analog behavior alongside event‑driven digital logic, improving model reuse and simulation fidelity.
Related Standards
- IEC 61691‑1‑1 / IEEE Std 1076 - Base VHDL language on which VHDL‑AMS is built.
- IEEE Std 1076.1‑2017 - the IEEE counterpart incorporated into IEC 61691‑6:2021.
IEC 61691‑6:2021 is available from IEC and IEEE publication channels for organizations requiring the official standard text.
