Overview
IEC 61691-7:2009 (Behavioural languages - Part 7: SystemC R Language Reference Manual) is an international standard published by the International Electrotechnical Commission (IEC). This standard precisely defines the SystemC® class library, which extends ANSI standard C++ for system and hardware design. By establishing a comprehensive reference, IEC 61691-7:2009 ensures consistent and interoperable implementations of SystemC, supporting the modeling, simulation, and verification of hardware and embedded systems.
SystemC provides essential language constructs to enable high-level design, simulation, and communication modeling. The IEC 61691-7:2009 standard aligns closely with IEEE Std 1666-2005 and serves as the primary specification for developers, tool vendors, and engineers utilizing SystemC for electronic system-level (ESL) design.
Key Topics
IEC 61691-7:2009 covers the following core areas related to SystemC and its application in system and hardware design:
- Scope and Purpose: Provides the objectives and intended use of the SystemC class library in hardware and system modeling.
- Relationship with C++: Explains SystemC's foundation as an ANSI C++ extension and how it integrates with existing C++ codebases.
- SystemC Class Library: Details core language constructs, including modules, processes, ports, signals, events, channels, and timing.
- Simulation and Elaboration Semantics: Specifies how SystemC simulations are executed and managed, from design instantiation to simulation callbacks.
- Syntax and Semantic Conventions: Outlines terminology, notational rules, and conventions for interpreting the language reference.
- Core and Channel Classes: Describes standard class definitions for modules, signals, clocks, buffers, ports, exports, and resolved signals.
Applications
Adopting IEC 61691-7:2009 offers significant value for a wide range of electronics and system-level design use cases, including:
- Hardware/Software Co-Design: Facilitates concurrent development and verification of hardware and software, bridging gaps between system architects and engineers.
- System-Level Modeling: Enables abstract, high-level modeling of entire systems, including interconnects, peripherals, and IP blocks.
- Simulation and Verification: Provides a standardized simulation engine for validating functional correctness and timing behavior before hardware synthesis.
- IP Integration: Supports integration and validation of reusable intellectual property (IP) modules in C++-based environments.
- Tool Interoperability: Ensures compatibility and uniformity across EDA tools, fostering ecosystem growth for system modeling and design automation.
By providing a universally recognized definition of SystemC, IEC 61691-7:2009 empowers organizations to reduce development risk, accelerate verification, and improve design portability and maintainability.
Related Standards
IEC 61691-7:2009 is part of a broader set of international standards supporting electronic design automation and modeling:
- IEEE Std 1666-2005: The base IEEE standard for SystemC, closely aligned and referenced within IEC 61691-7.
- IEC 61691 Series: Other parts of the IEC 61691 series cover various aspects of behavioural languages in system and hardware design.
- ANSI/ISO/IEC C++ Standards: The foundational standard for the C++ language, upon which SystemC is built.
- IEEE 1800 (SystemVerilog): A complementary standard for system-level and RTL modeling, providing alternative or combined workflows with SystemC.
- Other IEC/IEEE Hardware Description Language (HDL) standards: Such as those for VHDL (IEC 61691-1) and Verilog.
For system architects, hardware designers, and tool developers, compliance with IEC 61691-7:2009 ensures access to a widely recognized, robust, and extensible foundation for next-generation system design and verification.
Keywords: SystemC, IEC 61691-7:2009, hardware modeling, behavioural languages, C++ class library, hardware description, system simulation, EDA standards.
