Overview
IEC 63011-1:2018 is an international standard from the International Electrotechnical Commission (IEC) that establishes standardized terminology for three-dimensional integrated circuits (3D ICs). This document provides essential definitions related to multichip integrated circuits, specifically those employing vertically stacked dies interconnected with through-silicon vias (TSVs) or micro bumps. It serves as a foundational reference for stakeholders in semiconductor design, manufacturing, assembly, and testing of 3D integrated circuit technology.
Understanding the commonly accepted terms and definitions is critical for clear communication and streamlined processes across the global electronics and semiconductor industries. IEC 63011-1:2018 facilitates alignment and consistency in documentation, technical specifications, and quality assurance involving advanced 3D IC structures.
Key Topics
IEC 63011-1:2018 covers a comprehensive range of concepts integral to three-dimensional integrated circuits, including:
- Vertically Stacked Dies: Definitions related to the stacking of multiple semiconductor dies for enhanced density and performance.
- Through-Silicon Vias (TSVs): Terminology for TSV types (e.g., power TSV, single-drop signal TSV, multiple-drop signal TSV), functioning as vertical electrical connections in stacked devices.
- Micro Bumps and Interposers: Terms for micro bumps (small conductive spheres) and interposers (electrical interfaces connecting different components).
- 3D Bonding and Stacking: Processes that join dies or wafers together, ensuring electrical and mechanical integration.
- 3D Packaging and Test Methods: Coverage of packaging techniques (such as package-on-package, multi-chip-package) and definitions for various test environments and methods in 3D structures.
- Advanced Integration Methods: Clarification on concepts like system in package (SiP), die stack, flip chip, redistribution layer (RDL), and more.
- Non-contact Interconnects: Definitions involving connectivity through capacitive and inductive coupling, without physical electrical contact.
- Performance Considerations: Terms associated with reliability and signal integrity, such as cross talk, electromagnetic immunity, thermal immunity, and timing delay through TSVs.
Applications
IEC 63011-1:2018 terminology is valuable across a wide range of practical applications in the electronics industry, such as:
- Semiconductor Device Design: Enables engineers and designers to clearly specify requirements for advanced 3D integration and packaging technologies.
- Manufacturing and Assembly: Assists production teams in implementing and documenting processes related to stacked IC fabrication and testing with precise terminology.
- Testing and Quality Assurance: Standardizes communication around test methodologies for complex 3D environments, critical for ensuring product reliability and performance.
- Supply Chain Coordination: Promotes consistency among suppliers, manufacturers, and OEMs by providing a shared vocabulary for procurement and specification of 3D IC components.
- Research and Development: Supports R&D efforts in developing new types of 3D integrated circuits by providing a recognized foundation for technical discussions and innovation.
- Documentation and Training: Serves as a reference for creating manuals, datasheets, and educational materials for engineers and technicians.
Related Standards
Several IEC and international standards complement IEC 63011-1:2018, providing additional guidance for design, alignment, and testing of three-dimensional integrated circuits:
- IEC 63011-2: Integrated circuits - Three dimensional integrated circuits - Part 2: Alignment of stacked dies having fine pitch interconnect
- IEC 63011-3: Integrated circuits - Three dimensional integrated circuits - Part 3: Model and measurement conditions of through-silicon via
- IEC Electropedia: The IEC’s online electrotechnical vocabulary, which includes terms from this and related standards
- IEC 60050 Series: International Electrotechnical Vocabulary, covering general concepts in circuit theory, electromagnetic compatibility, and more
Adhering to these standards ensures harmonization and interoperability within the fast-evolving field of 3D IC technology.
Keywords: 3D integrated circuits, through-silicon vias (TSV), multichip ICs, micro bumps, 3D packaging, semiconductor terminology, IEC 63011-1, stacked dies, interposer, die stacking, electronic standards.
