Overview
IEC 60191-6-17:2011 is an international standard published by the International Electrotechnical Commission (IEC) that addresses the mechanical standardization of semiconductor devices, specifically for surface mounted semiconductor device packages. This part of the IEC 60191 series provides comprehensive guidelines and general rules for preparing outline drawings of stacked packages including fine-pitch ball grid array (FBGA) and fine-pitch land grid array (FLGA) packages, denoted as P-PFBGA and P-PFLGA.
The standard targets the design, dimensions, and interchangeability of individual stackable semiconductor packages and stacked assemblies, playing a crucial role in enabling the miniaturization and high-density integration demanded by modern portable electronic devices.
Key Topics
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Scope and Purpose
IEC 60191-6-17 standardizes the mechanical outlines and dimensional requirements for stacked semiconductor packages in FBGA and FLGA forms. It ensures that individual stackable packages can be combined efficiently in stacked configurations without mechanical incompatibilities.
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Definitions and Terminology
The document defines key terms such as individual stackable package, stacked package, mould cap height, upper side land grid pitch, coplanarity, and others essential for a uniform understanding of the mechanical features of stacked packages.
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Outline Drawings and Dimensioning
It provides detailed outline drawings with views from the top, side, and bottom, describing ball and land terminal placements, package heights, and spacing. These drawings help designers adopt standard dimensions to guarantee compatibility.
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Terminal Position Numbering
A systematic terminal grid numbering system is defined for easy identification and reference to terminal locations on packages. Rows use letters (excluding I, O, Q, S, X, and Z) and columns use numbers.
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Design Guidelines for Stacked Packages
The guide addresses stacking configurations including cavity-up and cavity-down packages and their combinations to support different design needs. Dimensions for different pitch sizes-from 0.30 mm to 0.80 mm-are also included.
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Dimensional Tables
The standard features extensive tables that specify mechanical parameters such as package height, ball diameters, pitch, and spacing dimensions, which are critical for mechanical design and verification.
Applications
IEC 60191-6-17:2011 is vital for:
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Semiconductor Package Designers
Engineers designing new FBGA and FLGA packages benefit from standardized mechanical outlines to ensure stackability and compatibility with existing products.
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Electronic Device Manufacturers
Manufacturers of mobile phones, tablets, and other compact electronics rely on these standards for developing smaller, high-functionality devices with multi-layer semiconductor packages.
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PCB Designers and Assembly
Printed circuit board designers use the specifications to accurately place stackable packages ensuring reliable mounting and electrical connection.
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Quality and Compliance Testing
Testing laboratories utilize the standardized dimensions and definitions to verify compliance and mechanical interchangeability of stacked semiconductor devices.
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Component Suppliers and Buyers
Standardized dimensions facilitate procurement and integration into supply chains by guaranteeing component interchangeability.
Related Standards
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IEC 60191-6: General rules for the preparation of outline drawings for surface mounted semiconductor device packages, serving as the foundational document for Part 6-17.
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IEC 60191-6-5: Design guide dedicated to fine-pitch ball grid array (FBGA) packages, closely related to the design principles for individual stackable FBGA packages referenced in Part 6-17.
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ISO/IEC Directives, Part 2: Governs the drafting principles of international standards including IEC publications.
Keywords
Mechanical standardization, semiconductor devices, surface mounted packages, stacked packages, fine-pitch ball grid array, fine-pitch land grid array, FBGA, FLGA, outline drawings, package design guide, terminal position numbering, semiconductor device dimensions, package stacking technology, miniaturization, electronic device packaging.
By adhering to IEC 60191-6-17:2011, industry professionals ensure consistent mechanical designs for stacked semiconductor packages, thus supporting the evolving demand for compact, high-density electronic devices in global markets.
Open preview (PDF)Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
